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Micrel Inc.
SQUELCH Decode
MICRF221
DOUT
CLK
Edge
Detector
Data Edge Pulses
Window
Counter
CLK
D
8 Stage
Shift Register
<=4
Good
>=7
Good
S
R
Q
SQUELCH
Disables DO
CLK
Bit
Window
Decode
CLK
Auto Poll
Decode
Bad Bits
Good
QA1 Bad Bit
Returns to
SLEEP
WATCHDOG
Timer
S
Decode Good
Bit Count
D7 D8
Select 0, 2, 4, 8 Good
Bits Before Wakeup
WAKEUP
Timer (300μs)
R
Serial Control Register
D15
D15 = 0 for Normal Operation
D15 = 1 for Auto Polled Operation
Figure 4. MICRF221 Autopoll-Bitcheck-Block Diagram
Auto-Polling
The auto-poll block (Figure 4) contains a low power
oscillator to drive the sleep timer when the rest of the
device is powered down, plus circuits to check
whether the received bits are good. Auto-polling is
controlled by bit D15 in the serial register, in
conjunction with bits D12,13,14 to set the sleep timer
period. Bits D7, D8, are used for control of the
bitchecking operation and bits D9, D10, D11 are used
to adjust the sensitivity of the bitcheck action.
For simple auto-polling without bitchecking, send a
serial command with bit 15 set high and bits D12,
D13, D14 set to the desired sleep time. The device
will go to sleep for the programmed timer duration
then wake up to receive data if present. Device will
stay awake until serial bit D15 is set low then set high
again to enable a further sleep period. Sleep duty
cycle may be controlled by the timing of serial
commands.
For polling with bitchecking the serial register bits
D7and D8 need to be set for the number of bits to be
checked as good, before the receiver outputs data at
the DO pin. The bitcheck window bits D9, D10, D11
must also be set to match the data period. The
default shortest window time gives the least critical
bitcheck action. For better discrimination, the window
setting may be increased up towards the normal
minimum time expected between data edges. Note
that a window time set longer than this will result in all
bits being tested as bad and the device will remain in
sleep polling mode. Now when the serial command is
sent to set bit D15 high the device will go to sleep for
the timer period, then will start to receive and check
bits. The device will output data again at DO as soon
as the programmed number of good RTZ bits have
been received. If a bad bit is seen the device will
return to sleep mode and poll again for good data
after the timeout period. Both high and low periods
are checked for each RTZ bit. If data transitions are
not received the device will return to sleep after the
bitcheck watchdog timeout period unless bit D18 has
been sent, in which case the device will continue to
check bits until sufficient good bits enable the device
to wake up, or bad bits return the device to sleep.
October 2008
10
M9999-100108
(408) 955-1690
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